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CAlex's avatar
CAlex
Icon for Contributor rankContributor
3 years ago
Solved

Can't debug the spl for cycloneVsoc dev kit

Hi, I followed the insruction on Rocketboards.org hwlib for cycloneVsoc on the environment of Quartus PRIME 18.1, soceds 22.1. I failed to debug the spl made from my project,here is the error infor...
Hps Boot
  • CAlex's avatar
    CAlex
    3 years ago

    Hi,

    I solve the problem,

    It is duel to the unfunctional of the PLL setting of FPGA.

    I ignored the SDC warning caused this problem.

    Sorry to take your time, please do whatever you need to this thread.

    Thank you.

EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thanks for the update. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



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