Forum Discussion

CAlex's avatar
CAlex
Icon for Contributor rankContributor
3 years ago
Solved

Can't debug the spl for cycloneVsoc dev kit

Hi, I followed the insruction on Rocketboards.org hwlib for cycloneVsoc on the environment of Quartus PRIME 18.1, soceds 22.1. I failed to debug the spl made from my project,here is the error infor...
Hps Boot
  • CAlex's avatar
    CAlex
    3 years ago

    Hi,

    I solve the problem,

    It is duel to the unfunctional of the PLL setting of FPGA.

    I ignored the SDC warning caused this problem.

    Sorry to take your time, please do whatever you need to this thread.

    Thank you.

EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


I may have seen similar issue before, I will need to do some dig in again. I shall get back to you.


CAlex's avatar
CAlex
Icon for Contributor rankContributor
3 years ago

Hi,

I solve the problem,

It is duel to the unfunctional of the PLL setting of FPGA.

I ignored the SDC warning caused this problem.

Sorry to take your time, please do whatever you need to this thread.

Thank you.