Forum Discussion
New ContributorCache coherency on Agilex 5 when booting secondary cores without ATF
I would suggest that you boot through the default bootloaders into your application so you can leverage all of the default configurations that they apply to the HPS for you, rather than trying to accurately replicate that in your own custom boot sequence. The FSBL which can be the ATF bl2 code but is typically the u-boot-spl code, will configure the HPS in general, ensuring that the HPS handoff data is correctly applied to the HPS, which gets the clocking and HPS IO and HPS EMIF all configured as the HPS was configured to operate in the Quartus project, and then it configures all the secure registers in the firewalls and things like that to get the HPS in the operational state that you expect. Then it passes control to the ATF bl31 code which finishes configuring the DSU and CPU cluster for proper default behavior. You would need to replicate all of that functionality in your own custom boot sequence to bring things up to a similar state.
If you need to use group 0 GIC interrupts, then you'll need to configure those from a secure state. Your realistic options are secure EL3 or secure EL1. To do this in S-EL3 state with the ATF code present, you'd be better served to apply your own customizations into the ATF code base and interact with your NS-EL2 application. To do this in S-EL1 state with the ATF code present, you'd need to start your secondary core and it's application to enter S-EL1 state and then operate from there.
Occasional ContributorI would suggest that you boot through the default bootloaders into your application so you can leverage all of the default configurations that they apply to the HPS for you, rather than trying to accurately replicate that in your own custom boot sequence. The FSBL which can be the ATF bl2 code but is typically the u-boot-spl code, will configure the HPS in general, ensuring that the HPS handoff data is correctly applied to the HPS, which gets the clocking and HPS IO and HPS EMIF all configured as the HPS was configured to operate in the Quartus project, and then it configures all the secure registers in the firewalls and things like that to get the HPS in the operational state that you expect. Then it passes control to the ATF bl31 code which finishes configuring the DSU and CPU cluster for proper default behavior. You would need to replicate all of that functionality in your own custom boot sequence to bring things up to a similar state.
If you need to use group 0 GIC interrupts, then you'll need to configure those from a secure state. Your realistic options are secure EL3 or secure EL1. To do this in S-EL3 state with the ATF code present, you'd be better served to apply your own customizations into the ATF code base and interact with your NS-EL2 application. To do this in S-EL1 state with the ATF code present, you'd need to start your secondary core and it's application to enter S-EL1 state and then operate from there.
New ContributorThank you for the explanation.
For my purpose, I believe getting a core into S-EL1 would be the best solution. What would you recommend as the best way to achieve this?
I have found two possible options: running a secure OS entirely in S-EL1, or extending the BL32 stage by using the Trusted Secure Payload (TSP) as a starting point.
If it is supported, booting our custom OS directly into S-EL1 would be my preferred approach. However, I haven’t yet worked out how to set this up. Are there any guides or resources you could point me to?
I am also experimenting with extending the TSP to run on the Agilex 5 HPS so that I can add my code there. Is this a reasonable alternative, or is there a more straightforward way to run code at S-EL1?
