Agilex5 EMAC to Fabric

I am trying to instantiate EMAC's that can be accessed over the Fabric:

This builds successfully in the Qsys - however when adding it to the top level Verilog GHRD:

...
wire outclk0_clk_wire; // 125MHz clock for Gb/s ethernet 

// emac0 definitions
wire emac0_app_rst_reset_n_wire, emac0_mac_tx_clk_o_wire, emac0_mac_tx_clk_i_wire, emac0_mac_rx_clk_wire, emac0_mac_rst_tx_n_wire, emac0_mac_rst_rx_n_wire;
wire emac0_mac_txen_wire, emac0_mac_txer_wire, emac0_mac_rxdv_wire, emac0_mac_rxer_wire, emac0_mac_col_wire, emac0_mac_crs_wire;
wire [7:0] emac0_mac_rxd_wire;
wire [2:0] emac0_mac_speed_wire;
wire [7:0] emac0_mac_txd_o_wire;

// emac1 definitions
wire emac1_app_rst_reset_n_wire, emac1_mac_tx_clk_o_wire, emac1_mac_tx_clk_i_wire, emac1_mac_rx_clk_wire, emac1_mac_rst_tx_n_wire, emac1_mac_rst_rx_n_wire;
wire emac1_mac_txen_wire, emac1_mac_txer_wire, emac1_mac_rxdv_wire, emac1_mac_rxer_wire, emac1_mac_col_wire, emac1_mac_crs_wire;
wire [7:0] emac1_mac_rxd_wire;
wire [2:0] emac1_mac_speed_wire;
wire [7:0] emac1_mac_txd_o_wire;

// Qsys Top module
qsys_top soc_inst(
...	
	 .iopll_0_outclk0_clk                               (outclk0_clk_wire),
	 .subsys_hps_agilex_hps_emac0_app_rst_reset_n       (emac0_app_rst_reset_n_wire),       
	 .subsys_hps_agilex_hps_emac0_mac_tx_clk_o          (emac0_mac_tx_clk_o_wire),
	 .subsys_hps_agilex_hps_emac0_mac_tx_clk_i          (emac0_mac_tx_clk_i_wire),
	 .subsys_hps_agilex_hps_emac0_mac_rx_clk            (emac0_mac_rx_clk_wire),
	 .subsys_hps_agilex_hps_emac0_mac_rst_tx_n          (emac0_mac_rst_tx_n_wire),
	 .subsys_hps_agilex_hps_emac0_mac_rst_rx_n          (emac0_mac_rst_rx_n_wire),
	 .subsys_hps_agilex_hps_emac0_mac_txen              (emac0_mac_txen_wire),
	 .subsys_hps_agilex_hps_emac0_mac_txer              (emac0_mac_txer_wire),
	 .subsys_hps_agilex_hps_emac0_mac_rxdv              (emac0_mac_rxdv_wire),
	 .subsys_hps_agilex_hps_emac0_mac_rxer              (emac0_mac_rxer_wire),
	 .subsys_hps_agilex_hps_emac0_mac_rxd               (emac0_mac_rxd_wire),
	 .subsys_hps_agilex_hps_emac0_mac_col               (emac0_mac_col_wire),
	 .subsys_hps_agilex_hps_emac0_mac_crs               (emac0_mac_crs_wire),
	 .subsys_hps_agilex_hps_emac0_mac_speed             (emac0_mac_speed_wire),
	 .subsys_hps_agilex_hps_emac0_mac_txd_o             (emac0_mac_txd_o_wire),
	 
	 .subsys_hps_agilex_hps_emac1_app_rst_reset_n       (emac1_app_rst_reset_n_wire),
	 .subsys_hps_agilex_hps_emac1_mac_tx_clk_o          (emac1_mac_tx_clk_o_wire),
	 .subsys_hps_agilex_hps_emac1_mac_tx_clk_i          (emac1_mac_tx_clk_i_wire),
	 .subsys_hps_agilex_hps_emac1_mac_rx_clk            (emac1_mac_rx_clk_wire),
	 .subsys_hps_agilex_hps_emac1_mac_rst_tx_n          (emac1_mac_rst_tx_n_wire),
	 .subsys_hps_agilex_hps_emac1_mac_rst_rx_n          (emac1_mac_rst_rx_n_wire),
	 .subsys_hps_agilex_hps_emac1_mac_txen              (emac1_mac_txen_wire),
	 .subsys_hps_agilex_hps_emac1_mac_txer              (emac1_mac_txer_wire),
	 .subsys_hps_agilex_hps_emac1_mac_rxdv              (emac1_mac_rxdv_wire),
	 .subsys_hps_agilex_hps_emac1_mac_rxer              (emac1_mac_rxer_wire),
	 .subsys_hps_agilex_hps_emac1_mac_rxd               (emac1_mac_rxd_wire),
	 .subsys_hps_agilex_hps_emac1_mac_col               (emac1_mac_col_wire),
	 .subsys_hps_agilex_hps_emac1_mac_crs               (emac1_mac_crs_wire),
	 .subsys_hps_agilex_hps_emac1_mac_speed             (emac1_mac_speed_wire),
	 .subsys_hps_agilex_hps_emac1_mac_txd_o             (emac1_mac_txd_o_wire)
);
...

The compilation process exits at the fitting stage with the following issue:

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 NOC_FABRIC_ADAPTOR(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number. 
	Error(175001): The Fitter cannot place 1 NOC_FABRIC_ADAPTOR, which is within External Memory Interfaces for HPS Intel FPGA IP emif_hps_emif_hps_ph2_610_r3atsia. 
		Error(16234): No legal location could be found out of 8 considered location(s).  Reasons why each location could not be used are summarized below: 
			Error(175006): There is no routing connectivity between the NOC_FABRIC_ADAPTOR and destination HMC 
				Error(175022): The NOC_FABRIC_ADAPTOR could not be placed in any location to satisfy its connectivity requirements 
			Error(175006): There is no routing connectivity between the NOC_FABRIC_ADAPTOR and destination SOC_HPS 
				Error(175022): The NOC_FABRIC_ADAPTOR could not be placed in any location to satisfy its connectivity requirements 
Error(15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action. 
Error(16297): An error has occurred while trying to initialize the plan stage. 

Any pointers on what I have done wrong would be greatly appreciated!