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Moti_Tawil's avatar
Moti_Tawil
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5 months ago

Agilex 7 dk_si_agi027fa FPGA issue

Hello.

My name is Moti. I am working on a project with agilex 7 that requires me to create a driver to communicate with the FPGA registers of agilex 7 dk_si_agi027fa.

The first step was to build GSRD for this board. We followed the instructions in this page:

https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/i-series/soc/gsrd/ug-gsrd-agx7i-soc/#build-flow

We flashed the results (u-boot, fs and linux images) to an sd card, and I was able to bring up linux on the board with a sample driver (that works properly).

Unfortunately, I wasn't able to communicate with any fpga registers.

The following output:
root@MiWiFi-RA80-srv:~# cat /sys/class/fpga_manager/fpga0/state
unknown
leads us to understand that the .rbf file wasn't loaded properly, and needs to be loaded into the board.
(state "unknown" means fpga is not configured -> probably because the .rbf file wasn't loaded).
we want to ask:
- Is that the correct next step?
- I am using agilex7_dk_si_agi027fa_gsrd_ghrd.core.rbf as mentioned in GSRD - is that the correct one?
- how do I load the .rbf? i tried following instructions from the web - copied it to the sd card and ran the following command, but I keep receiving "error 4":
SOCFPGA_AGILEX # fatload mmc 0:1 0x2000000 agilex7_dk_si_agi027fa_gsrd_ghrd.core.rbf
1658880 bytes read in 77 ms (20.5 MiB/s)
SOCFPGA_AGILEX # fpga load 0 0x2000000 ${filesize}
..
U-Boot SMC: Error sending bitstream! SDM: Config status: (0xf0040000) SDM Err: Bitstream element not understood. Internal error. Catchall Error. Command 'load' failed: Error 4
I also noticed fpga fails to load during boot and the errors seem similar to the ones i get when i try to manually load the .rbf file:
## Loading fpga from FIT Image at 02000000 ...
Trying 'fpga-4' fpga subimage
 Description: FPGA bitstream for GHRD
Type: FPGA Image
Compression: uncompressed
Data Start: 0x0297e764
Data Size: 1658880 Bytes = 1.6 MiB
Load Address: 0x0a000000
Hash algo: crc32
Hash value: 654d6710
Verifying Hash Integrity ... crc32+ OK
Loading fpga from 0x0297e764 to 0x0a000000
..
U-Boot SMC: Error sending bitstream!
SDM: Config status: (0xf0040000)
SDM Err: Bitstream element not understood. Internal error.
Catchall Error.
..
U-Boot SMC: Error sending bitstream!
SDM: Config status: (0xf0040000)
SDM Err: Bitstream element not understood. Internal error.
Catchall Error.
FPGA image is corrupted or invalid
Your assistance on the above will be much appreciated.
Thanks.
Configuration

7 Replies

  • Moti_Tawil's avatar
    Moti_Tawil
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    5 months ago

    The issue has been resolved by aligning the Quartus versions.

    Thanks for the feedback!

    Moti

  • KianHinT_altera's avatar
    KianHinT_altera
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    5 months ago

    Hi Moti

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Do feel free to create another thread as well if you still have further issues after you tested the build using the same Quartus version.

    Thanks

    Regards

    Kian

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    5 months ago

    Hi Moti,

    Just wondering whether your issue have been resolved after using the same Quartus version?

    Thanks

    Regards

    Kian

  • Moti_Tawil's avatar
    Moti_Tawil
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    5 months ago

    Hey, thanks for the replies.

    It turns out the JIC file we used was created with Quartus 24.3.1, while the Linux image build flow was done with version 25.1. We're now aligning the versions to match and will try again.

    Regards

    Moti

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    5 months ago

    Hi Moti,

    Could you tell the Quartus version that you're using ?

    Thanks

    Regards

    Kian

  • alifzakuan_altera's avatar
    alifzakuan_altera
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    5 months ago

    Hi Moti,

    I would suspect that this is due to a mismatch between your Quartus and GHRD versions.

    Can you help to confirm on which Quartus version you are running?

    Thanks,

    Alif

  • Moti_Tawil's avatar
    Moti_Tawil
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    5 months ago

    Hello,

    I want to simplify the issue:

    First, we followed the GSRD user guide instructions:

    https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/i-series/soc/gsrd/ug-gsrd-agx7i-soc/#boot-linux_1

    - We made sure we follow it precisely - we went over it 4-5 times.

    - Linux boots properly, we have ssh access, and we have serial access (with minicom).

    - We can run the sample scripts and we can use the ssh GUI (even though they don't provide the expected LED outputs).

    The first part that fails is "Running Sample Applications". "Hello World" works, but the fpga related samples don't work - toggling leds from the sample scripts, and toggling leds from the ssh.

    (the http gui opens properly, but providing some input - like to toggle every 100ms - doesn't show any result).

    My first post shows some solutions I tried and outputs to commands that should work, according to what I saw in the web, and it seems that fpga wasn't configured correctly.

    Is there anything we can try, or is there some way to know at what part we are failing? What can be the next step of investigation?

    Assitance will be much appreciated.

    Thank you.