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SarahTr's avatar
SarahTr
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2 months ago

Agilex 5 HPS EMAC2 SWR bit in DMA_Mode Register Not Clearing

Hello, Following section 5.1.7 of the Agilex 5 Hard Processor System Technical Reference Manual, and based on what I found in U-Boot and Linux, I am writing an Ethernet driver that uses EMAC2 with a...
Hps Debug
Sw Development
SarahTr's avatar
SarahTr
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1 month ago

Hello Kian,
Thank you for your reply.
The issue turned out to be missing IO control register configurations.
Our adaptations in the U-Boot to load INOS overwrote IO control register writes done in the boot command for the AXE5-Eagle board.
After adding them back in, the software reset worked.
Thanks,
Sarah

SueC_Altera's avatar
SueC_Altera
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1 month ago

Thanks for sharing your solution, SarahTr​! That's really helpful for the community!

Sue