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K606's avatar
K606
Icon for Contributor rankContributor
4 months ago

Agilex 5 GTS to HPS CDC/STA issue: help request!

I am trying to bring-up the GTS component on the A5. The general idea is: Oscillator -> GTS -> FIFO -> DMA -> HPS -> Application. The Qsys diagram looks as followed (HPS section omitted for brevity...
Hps Boot
RolandoS_Altera's avatar
RolandoS_Altera
Icon for Occasional Contributor rankOccasional Contributor
4 months ago

Hello K606

I am wondering if the issue could be related to IO HASH compatibility documented in https://www.intel.com/content/www/us/en/docs/programmable/813762/25-1/hps-io-hash-compatibility.html

There are several factors that could create this problem that affect the HPS Boot First boot mode. The main factors that could cause this issue is that the Quartus version used to create the PHASE 1 should be the same than the one used in PHASE2. The other factor that could cause this issue is that this IO HASH calculated from the configuration in the HPS Banks (including the HPS EMIF) mismatches between the PHASE1 and PHASE 2. So it's always recommended that if you rebuild the hardware design, you use the PHASE1(loaded from your jic image or transfered through JTAG) and PHASE2 (transfer with TFTP) from this new build.

There are many other causes that generate this issue, these are described in the document above. Please take a look to this to confirm or disscard that this could be the problem you are facing.

Thanks

Rolando