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K606's avatar
K606
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1 year ago
Solved

Agilex 5 EMAC to EMAC : Driver error

I am trying to ping one EMAC from another, and have instantiated the following in the HPS: These are exported to the top level, then connected as followed: // https://www.intel.com/content/...
Sw Development
  • K606's avatar
    K606
    1 year ago

    Solved: bring MAC signals up a module

TiensungA_Altera's avatar
TiensungA_Altera
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

On top of what my other colleagues asked, Can you also dump, the boot Linux log for all the lines that mentions "socfpga-dwmac"?

I want to understand if the Hard IP is even accessible or enabled correctly by the Quartus design for Ethernet. The example i have here is for gmac2. But you are using gmac0 and gmac1. It seems you are unable to even perform the initial setup of the ETH HW which has a DMA engine. This requires write to the ETH HW CSR register address.

I want to see if the GMAC0 and GMAC1 are even enabled correctly from the Quartus design at the HPS.

In the Quartus HPS config, did you enable GMAC0 and GMAC1 from the dropdowns to select the function?

GMAC0: → [ RGMII ] / [ SGMII ] / [ Disabled ]
GMAC1: → [ RGMII ] / [ SGMII ] / [ Disabled ]

This should be propagated as a handoff data to the U-boot HPS FSBL which will configure the PINMUX and also CLK settings. The Handoff is important to the HPS to configure the ETH clock settings and pinmux. The GMAC0 and GMAC1 reset should already been de-asserted by the U-boot during boot-up. So, i don't suspect the reset de-assertion. It is either the CLK or the PINMUX or a combination of both. Without CLK, the IP will be permanently be disabled. CLK is the major suspect.

In short, I suspect that, the GMAC0 and GMAC1 CLK are disabled by a bad Quartus configuration.

Log for Linux: Example for a working GMAC on GMAC2. I need to see the similar log for GMAC0 and GMAC1 on your end. I want to know how far it went before it threw the error.

[ 0.744790] socfpga-dwmac 10830000.ethernet: Adding to iommu group 0

[ 0.746937] socfpga-dwmac 10830000.ethernet: IRQ eth_wake_irq not found

[ 0.747646] socfpga-dwmac 10830000.ethernet: IRQ eth_lpi not found

[ 0.748310] socfpga-dwmac 10830000.ethernet: IRQ sfty not found

[ 0.749186] socfpga-dwmac 10830000.ethernet: SMTG Hub Cross Timestamp supported

[ 0.750124] socfpga-dwmac 10830000.ethernet: User ID: 0x76, Synopsys ID: 0x31

[ 0.750897] socfpga-dwmac 10830000.ethernet: XGMAC2

[ 0.751426] socfpga-dwmac 10830000.ethernet: DMA HW capability register supported

[ 0.752217] socfpga-dwmac 10830000.ethernet: RX Checksum Offload Engine supported

[ 0.753010] socfpga-dwmac 10830000.ethernet: COE Type 1

[ 0.753568] socfpga-dwmac 10830000.ethernet: TX Checksum insertion supported

[ 0.754310] socfpga-dwmac 10830000.ethernet: TSO supported

[ 0.754904] socfpga-dwmac 10830000.ethernet: Enabled L3L4 Flow TC (entries=16)

[ 0.755669] socfpga-dwmac 10830000.ethernet: Enabled RFS Flow TC (entries=10)

[ 0.756422] socfpga-dwmac 10830000.ethernet: TSO feature enabled

[ 0.757061] socfpga-dwmac 10830000.ethernet: SPH feature enabled

[ 0.757698] socfpga-dwmac 10830000.ethernet: Using 40/40 bits DMA host/device width

K606's avatar
K606
Icon for Contributor rankContributor
1 year ago

Hi Tiensung, thanks for the detailed response. Here is the dump you asked for:

root@localhost:~# dmesg | grep "socfpga-dwmac"
[    1.433914] socfpga-dwmac 10810000.ethernet: Adding to iommu group 0
[    1.440789] socfpga-dwmac 10810000.ethernet: IRQ eth_wake_irq not found
[    1.447387] socfpga-dwmac 10810000.ethernet: IRQ eth_lpi not found
[    1.453610] socfpga-dwmac 10810000.ethernet: RX VLAN HW Stripping
[    1.459766] socfpga-dwmac 10810000.ethernet: SMTG Hub Cross Timestamp supported
[    1.467356] socfpga-dwmac 10810000.ethernet: User ID: 0x76, Synopsys ID: 0x31
[    1.474476] socfpga-dwmac 10810000.ethernet:         XGMAC2
[    1.479421] socfpga-dwmac 10810000.ethernet: DMA HW capability register supported
[    1.486867] socfpga-dwmac 10810000.ethernet: RX Checksum Offload Engine supported
[    1.494311] socfpga-dwmac 10810000.ethernet: COE Type 1
[    1.499510] socfpga-dwmac 10810000.ethernet: TX Checksum insertion supported
[    1.506522] socfpga-dwmac 10810000.ethernet: TSO supported
[    1.511980] socfpga-dwmac 10810000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    1.519954] socfpga-dwmac 10810000.ethernet: device MAC address ca:3e:cc:fb:1a:6f
[    1.527409] socfpga-dwmac 10810000.ethernet: Enabled L3L4 Flow TC (entries=16)
[    1.534597] socfpga-dwmac 10810000.ethernet: Enabled RFS Flow TC (entries=10)
[    1.541696] socfpga-dwmac 10810000.ethernet: TSO feature enabled
[    1.547672] socfpga-dwmac 10810000.ethernet: SPH feature enabled
[    1.553647] socfpga-dwmac 10810000.ethernet: TX COE limited to 2 tx queues
[    1.560490] socfpga-dwmac 10810000.ethernet: Using 40/40 bits DMA host/device width
[    1.568244] socfpga-dwmac 10810000.ethernet (unnamed net_device) (uninitialized): failed to setup phy (-22)
[    1.578069] socfpga-dwmac: probe of 10810000.ethernet failed with error -22
[    1.585185] socfpga-dwmac 10820000.ethernet: Adding to iommu group 1
[    1.591958] socfpga-dwmac 10820000.ethernet: IRQ eth_wake_irq not found
[    1.598547] socfpga-dwmac 10820000.ethernet: IRQ eth_lpi not found
[    1.604742] socfpga-dwmac 10820000.ethernet: RX VLAN HW Stripping
[    1.610871] socfpga-dwmac 10820000.ethernet: SMTG Hub Cross Timestamp supported
[    1.618262] socfpga-dwmac 10820000.ethernet: User ID: 0x76, Synopsys ID: 0x31
[    1.625371] socfpga-dwmac 10820000.ethernet:         XGMAC2
[    1.630312] socfpga-dwmac 10820000.ethernet: DMA HW capability register supported
[    1.637756] socfpga-dwmac 10820000.ethernet: RX Checksum Offload Engine supported
[    1.645200] socfpga-dwmac 10820000.ethernet: COE Type 1
[    1.650400] socfpga-dwmac 10820000.ethernet: TX Checksum insertion supported
[    1.657412] socfpga-dwmac 10820000.ethernet: TSO supported
[    1.662870] socfpga-dwmac 10820000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    1.670837] socfpga-dwmac 10820000.ethernet: device MAC address 9a:56:d9:98:64:37
[    1.678288] socfpga-dwmac 10820000.ethernet: Enabled L3L4 Flow TC (entries=16)
[    1.685476] socfpga-dwmac 10820000.ethernet: Enabled RFS Flow TC (entries=10)
[    1.692576] socfpga-dwmac 10820000.ethernet: TSO feature enabled
[    1.698551] socfpga-dwmac 10820000.ethernet: SPH feature enabled
[    1.704526] socfpga-dwmac 10820000.ethernet: TX COE limited to 2 tx queues
[    1.711367] socfpga-dwmac 10820000.ethernet: Using 40/40 bits DMA host/device width
[    1.719030] socfpga-dwmac 10820000.ethernet (unnamed net_device) (uninitialized): failed to setup phy (-22)
[    1.728811] socfpga-dwmac: probe of 10820000.ethernet failed with error -22
[    1.735813] socfpga-dwmac 10830000.ethernet: Adding to iommu group 2
[    1.742511] socfpga-dwmac 10830000.ethernet: IRQ eth_wake_irq not found
[    1.749095] socfpga-dwmac 10830000.ethernet: IRQ eth_lpi not found
[    1.755277] socfpga-dwmac 10830000.ethernet: RX VLAN HW Stripping
[    1.761389] socfpga-dwmac 10830000.ethernet: SMTG Hub Cross Timestamp supported
[    1.768798] socfpga-dwmac 10830000.ethernet: User ID: 0x76, Synopsys ID: 0x31
[    1.775904] socfpga-dwmac 10830000.ethernet:         XGMAC2
[    1.780844] socfpga-dwmac 10830000.ethernet: DMA HW capability register supported
[    1.788288] socfpga-dwmac 10830000.ethernet: RX Checksum Offload Engine supported
[    1.795732] socfpga-dwmac 10830000.ethernet: COE Type 1
[    1.800930] socfpga-dwmac 10830000.ethernet: TX Checksum insertion supported
[    1.807942] socfpga-dwmac 10830000.ethernet: TSO supported
[    1.813399] socfpga-dwmac 10830000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    1.821365] socfpga-dwmac 10830000.ethernet: Enabled L3L4 Flow TC (entries=16)
[    1.828554] socfpga-dwmac 10830000.ethernet: Enabled RFS Flow TC (entries=10)
[    1.835654] socfpga-dwmac 10830000.ethernet: TSO feature enabled
[    1.841629] socfpga-dwmac 10830000.ethernet: SPH feature enabled
[    1.847605] socfpga-dwmac 10830000.ethernet: TX COE limited to 2 tx queues
[    1.854445] socfpga-dwmac 10830000.ethernet: Using 40/40 bits DMA host/device width
[    2.448680] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
[    2.457891] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-1
[    2.467051] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-2
[    2.476248] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-3
[    2.485428] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-4
[    2.494627] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-5
[    2.503864] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-6
[    2.513108] socfpga-dwmac 10830000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-7
[    2.589649] socfpga-dwmac 10830000.ethernet eth0: PHY [stmmac-2:01] driver [Micrel KSZ9031 Gigabit PHY] (irq=POLL)
[    2.600063] socfpga-dwmac 10830000.ethernet eth0: No Safety Features support found
[    2.607619] socfpga-dwmac 10830000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[    2.616428] socfpga-dwmac 10830000.ethernet eth0: registered PTP clock
[    2.623199] socfpga-dwmac 10830000.ethernet eth0: FPE workqueue start
[    2.629622] socfpga-dwmac 10830000.ethernet eth0: configuring for phy/rgmii-id link mode
[    6.724299] socfpga-dwmac 10830000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx

Additionally, here is the EMAC config:

I had assumed that since I am t using a PHY right now, I don't need to configure the PHY options - but perhaps the PHY needs to be set in either case?

Many thanks,

K