Thanks for sharing your Agilex 5 .dtsi file. The EMAC (gmac0/gmac1/gmac2) sections look well-defined, however, all three EMACs have status = "disabled";, so the kernel will not load drivers for them unless another .dts or .dtsi file (like a board-specific one) overrides this with status = "okay".
Example for gmac0:
&gmac0 {
status = "okay";
phy-mode = "rgmii"; // or "sgmii", "rmii" — depending on your design
phy-handle = <&phy0>; // reference to an external PHY if used
// Optional: fixed-link if no external PHY
fixed-link {
speed = <1000>;
full-duplex;
};
};
Make sure to also define &phy0 if you're using an external PHY. Confirm your boot .dtb includes a version of the EMAC node with status = "okay". Ensure clocks and reset lines are properly asserted and enabled by the bootloader or preloader stage.
The error message that you shared suggests that the DMA controller inside the EMAC IP block isn't initializing properly, likely because its reset line isn't working or hasn't been deasserted.
Couple of things to try:
Check the rst node is working
- Make sure the reset controller in your .dtsi is active and matches the hardware
- Ensure your kernel has altr,stratix10-rst-mgr driver enabled
- Check whether the IDs like EMAC0_RESET are correct (from altr,rst-mgr-agilex5.h)
Try without reset control (for debugging)
- Temporarily, remove the reset lines in the EMAC node to test if the problem is reset-controller-related -> If EMAC initializes without errors afterward, then the issue is definitely the reset controller.
Ensure EMAC is powered and clocked
- Even if resets are correct, clocks must be enabled
- Make sure, Clock controller (clkmgr) is active and functional
- These clocks are not gated or unconfigured by U-Boot or preloader - Use U-Boot to verify clock settings, or explicitly enable the clocks in bootloader
Enable only one EMAC first
- Only bring up gmac0 initially. In your board .dts
&gmac0 {
status = "okay";
phy-mode = "sgmii"; // or your actual mode
fixed-link {
speed = <1000>;
full-duplex;
};
};