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Altera_Forum
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12 years ago

Zero total logic elements for top module instantiate lower module

Hi all, I'm getting zero total logic elements in my top module compilation, if I set my lower level module set top level entity and compile it, there total logic elements showing some number. ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

A design that has no outputs basically does nothing. Hence why the synthesisor removes all logic. How do you expect to monitor it on the real FPGA if it has no outputs?