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Altera_Forum
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14 years ago

Yet Another Verilog Inconvenience

When trying to build a QSys module for my own building block I got the following error: --- Quote Start --- Error: Error: Error (10867): Verilog HDL or VHDL XML Interface error at sensor.vh...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

in my opinion, the std_logic_2d type was a fudge that was ****, that made it incompatible with any other code.

I dont quite understand why they didnt just do arrays like everything else - an array of std_logic_vectors.