XOR operator doesnt work?

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Im trying to code a 1bit CRA adder. here is my code.

LIBRARY ieee;USE ieee.std_logic_1164.ALL;
ENTITY CRA1BIT IS
        PORT(c0, x0, y0: IN std_logic;
                        s0, c1: OUT std_logic);
END CRA1BIT;
ARCHITECTURE s0func OF CRA1BIT IS
BEGIN
        s0 <= (c0 XOR x0 XOR y0);
END s0func;
ARCHITECTURE c1func OF CRA1BIT IS
BEGIN
        c1 <= ((x0 AND y0) OR (c0 AND (x0 OR y0)));
END c1func;

I have used modelsim and the waveform editor in Quartus 2 to check this and in both c1 works as it should but s0 gives me 0 all across the board. iv tried playing with parenthesis and even tried just doing x0 XOR y0 and that doesnt even work. Whats the problem here?

Thanks in advanced.

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and why two architectures???

an entity can have several architectures but all my life I never needed to go multiple.

In any case each architecture defines all outputs of entity.

I believe you wanted just to make sure!!! two is better than one.

You define two architectures for one entity. During simulation (or synthesis), only one will actually be used.

Quartus will use the last one it encounters if none is selected (hierarchy, configuration).

If you want both the statements to be executed (sim), or synthesized, put them in one architecture;

ARCHITECTURE func OF CRA1BIT IS

BEGIN

s0 <= (c0 XOR x0 XOR y0);

c1 <= ((x0 AND y0) OR (c0 AND (x0 OR y0)));

END func;

The use of multiple architecture is very handy if you want to describe behavior on different levels, such as RTL or logic.

You can test both and see if they behave the same.

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The use of multiple architecture is very handy if you want to describe behavior on different levels, such as RTL or logic.

You can test both and see if they behave the same.

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what for? one can hardly finish one design to the managers deadlines. It may be ok for research purposes.

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what for? one can hardly finish one design to the managers deadlines. It may be ok for research purposes.

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In the early days, when VHDL was created, there were no synthisizers available. At first, VHDL was only for simulating behavior.

Hardware design were done using graphical editors were you could place polysilicon, diffusion and metal layers, basically transistors and gates at the logic level.

So a designer would like to simulate on a high level but had to rewrite the design to a lower level and test if the behaviors are identical. VHDL supports this with multiple architectures.

Nowadays, there are synthesizes available that can synthesize from RT-level, so the need for multiple architectures is probably no longer needed.