Wrong results when running design on hardware

The first one is a standard load after store dependency. It will cause a race condition and potentially incorrect results on every hardware, not just FPGAs. Using atomic load/stores might bypass this problem, but that would be extremely slow to the point that it might be faster if you just serialize your loads and stores. If both operations are in the same kernel, the compiler will make sure to use the lowest-possible iteration interval to avoid the dependency. In the worst case, it will serialize them.

The second case is an incorrect code. I am redefining the same variable inside the loop, which will likely result in an error in standard C code (haven't tested) but for some reason, OpenCL compilers and also Altera's emulator seem to compile that code successfully (even though they shouldn't) and in a way that there is only one "sum" variable, while AOC [correctly] compiles the code in a way that there are two, with one of them only being valid inside of the loop. This case should not exist in any correct code; I have made this "mistake" a few times, though, and couldn't catch the mistake by using the emulator. Note that the cases I encountered this issue were a lot more complex, and the example I have used here might not actually show the problem (or it might outright fail to compile).