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I only tried doing this once, with multiple different barrier configurations, but none of the configurations worked in the end. Since debugging on the FPGA is too time-consuming and troublesome, and the emulator fails to correctly emulate and show this behavior, I gave up on that design and merged the two kernels into one to make sure I would get correct results. Even though the "CLK_GLOBAL_MEM_FENCE" seems to be supposed to avoid such race conditions, in practice it doesn't seem to work as intended. Note that the OpenCL specification does NOT guarantee global memory consistency unless at the end of kernel execution and hence, Altera doesn't have to provide the means to avoid such problems. I would suggest seeking an alternative kernel design. You could also open a ticket directly with Altera and ask them why the barrier is not working as it should, in this case.
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Merging kernels was the solution.
Thanks!
Honored Contributor
