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Altera_Forum's avatar
Altera_Forum
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11 years ago

Writing SDRAM from custom IP using Avalon MM write Template

Hello,

I want to write SDRAM through my custom hardware IP. I am using the Master Templates for this. I am writing using custom hardware and reading using NIOS, but my nios doesn't read the correct value.

Below is my code for writing into SDRAM.

I want to write on the click of a button (coe_switch[3]). I have one more doubt, "myBuffer_control_write_write_base" should be the base address for SDRAM or offset or base+offest.

reg searchForSync;
always @(posedge csi_clk or negedge rsi_rst) begin
if(!rsi_rst) begin
   click <= 0;
   searchForSync <= 0;
end else begin
   if(coe_switch == 0) begin
   searchForSync <= 1;
   myBuffer_control_write_fixed_location <= 0; 
   myBuffer_control_write_write_base <= 32'h00000000; 
   myBuffer_control_write_write_length <= 8; 
   myBuffer_control_write_go <= 1; 
   myBuffer_user_write_buffer_input_data <= 1;
   myBuffer_user_write_write_buffer <= 1;
end
if(searchForSync == 1) begin
   myBuffer_user_write_buffer_input_data <= 1;
   myBuffer_user_write_write_buffer <= 1;
   myBuffer_control_write_go <= 0;
end
end

Please let me know if I am doing something wrong.

Please suggest.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    As a_x_h_75 mentioned in the other thread, you haven't really given enough details to answer your question or help you. Post more code and give a better description of your problem (e.g. describe what you do read, and what the correct value should have been).

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hello,

    Above part of code is a part of my custom IP. I just want to write some data in SDRAM on click of a button as can be seen in the above code. I added this part to write some data in SDRAM. I am using Master Write Template in Qsys to do so. From my custom IP I am giving below signals to Master Write Template (IP in Qsys):

    myBuffer_control_write_fixed_location

    myBuffer_control_write_write_base

    myBuffer_control_write_write_length

    myBuffer_control_write_go

    myBuffer_user_write_buffer_input_data

    myBuffer_user_write_write_buffer

    Attached is the Qsys snap.

    Right now I am only considering the write operation. I have a top verilog file in which i connect the exported signal from my custom hardware to the exported signal from Master Write template. And Master Write template is directly connected to SDRAM.

    Please let me know if can help with more details.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    You don't seem to be processing the 'done' or 'full' signals.

    Also, your data is always '1' and it's not clear if that is intentional or not.

    If you continue to be stuck on this, I suggest creating a testbench and debugging in Modelsim as that will easily allow you to see what is getting written where.