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thanks! Your help really saves me...
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Hi,
50% off the required clock frequency will not work on the FPGA. You mentioned that you a have simulation of your complete design based on the speparate vqm files. Could you re-run this simulation with your single vqm file ? This is an important step, because if it rums we know that the source code is ok. Follow my recommendations in the previous post.
When you synthesize the blocks separately the tool needs to know the timing at the inputs and outputs. You have to keep in mind that you get paths between your blocks when you import them to your main project. Lets assume the driving block has an output and the receiving block an input register. When you now use retiming without constraints for the ports this register will be moved into your logic in order to achieve timing closure. But now
you have longer paths at the in- and outputs. Without a constraint the tool assumes e.g that the data arrives without any delay ( 0.0ns) to the active clock edge. In your real design that will be not true.
In SynplifyPro setting an input delay describes the delay outside of your block before the signal arrives the input pin. Output signals drives logic outside your of block. The tool needs a information about the delay.
You can set both in the scope table in the tab "Inputs/Outputs" or directly in the sdc -file:
define_input_delay {porta[7:0] 4.0 -ref clk:r
Kind regards
GPK
Honored Contributor
