working with Quartus 8+Synplify DSP + Synplify PRO

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Hi,

I understand that you did not achieve the required clock frequency when you synthezise the design as a whole. How far are you away from the target ? If the difference is around 15-20% of the target you can still try to run the on the FPGA. The reason is that the default timing analysis is worst-case. That means low core voltage, highest temperature and slowest production process. If the design is running we can be sure that the design itself is ok. If the gap is too large or the design isn't running run a simulation of the design.

As default the Quartus simulator uses a netlist with timing. Therefore you should reduce the clock frequence in the simulation. You can do that, because for the simulation results it is not important how fast the clock is. Alternativ you can run a functional simulation. For such simulation you have to generate an appropriate netlist. This could be done in the Quartus simulator. If this works we can also be sure that the design is ok.

the difference was quite large (approx. 50%), i did put it on the fpga but i got weird results on the screen - i thought they were because of the timing...

Coming back to your hierachy. I understand following:

manufaturer_toplevel

-> "high hierachyfile.bdf" (Your toplevel)

-> DSP1,DSP2,MEM1,DSP3,MEM2

correct.

the high hierarchy file contains more then just what listed on the bottom - but that's not relevant (i think).

First you put high hierachyfile.bdf with all submodule in one project. Then you changed

to separate vqm (Partitions) for DSP1,DSP2,MEM1,DSP3,MEM2 in order to achieve the

timing.

yes.

Now some questions about the retiming with SynplifyPro. When you synthesized the module separately, did you set a constraint for the inputs and outputs ? If not , SynplifyPro moves the registers without looking to input and output delays. As result it is possible that you get too long paths at the inputs and outputs after importing the design.

To overcome this I would set tough requirements for input and output delays. Play a little

bit with the clock frequency setting, but avoid over-constraining.

could you elaborate on that? all i did is setup a minimum frequency (which was about twice the frequency i need when i synthesized each part separately , and in the log i could see that it does achieve this frequency.

how do i constrain the input\output correctly?

when i synthesized the entire project i set the min. freq. to be the actual min. freq. (because when i set it for higher - it didn't come even close to that) - and i didn't get my actual min. freq.

just to be clear - i'm talking about 25.18mhz as my absolute minimum frequency.

Did you try for the whole design SynplifyDSP verilog output. Maybe retiming works better with verilog.

i did use verilog - i got the same results...

Kind regards

GPK

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thanks! Your help really saves me...