Honored Contributor
Honored Contributorin the log i can see how much register levels it has inserted - when i do this separately i end up with approx 80 register levels, but when i do this on the entire project - all i get is less than 10.
because of that i thought that synplify must have problems with large designs - and went on to splitting it.
2. In order to achieve timing closure you split your design and introduced an "external" memory. Is that memory outside of the FPGA or means "external" it is outside your original design ? How did you split the design ? i'm now using internal memory (fpga mram and m4k) - but eventually i would have to use onboard ddrii memory. i use the memory to implement parts of the algorithm (like transpose operation and flips etc... ) the design was actually split all the time - two parts of synplifydsp, memory part, another synplifydsp part and finally another memory part. what i did in the beginning is importing the entities of the memory blocks into synplifydsp (as black boxes) and synthesizing the entire project in synplify, getting a large vqm (that includes the memory + synplify) that i inserted into quartus and then i have done a p&r- this ended up with low frequency.
i then started from the beginning: went to quartus - and built there the entire project again - this time importing the smaller synplify parts into quartus (at first - as vqm, later - as design partitions)
i compile, and after successful p&r i load to the fpga - and it doesn't work.
You run two SynplifyDSP ( generates the VHDL ) and SynplifyPro (generates the vqm files) projects. After that you run two speparate Quartus project in order to synthesis the two blocks ( necessary due to the module name problems of SynplifyDSP). After that you import the two blocks into your main project as <>.qxp file. You run a simulation for each block using the vqm file generated by SynplifyPro. After solving some problems ( implementation as LE, switch from VHDL to verilog) the simulation shows the expected results. yes. 3. For your main project you need a toplevel. How is it generated ? Did you run a simulation of the main project with the imported blocks included ? Which simulator do use for simulation Quartus or modelsim ? i use the built in simulator in quartus. i have a top level file which i get from the card manufacturer, which calls a file that for me -the highest file in the hierarchy that i can still change.
this "high hierarchy file" is actually a .bdf file, that connects the entire parts, from input to output.
every part - because i had to find a way to incintiate it - i created (manually) a .bdf file which holds only inputs and outputs, same as are in the qxp creating projects.
simulation of the main project - don't work. i get exactly as i what i'm seeing in signaltap - a lot of pins are stuck at vcc/gnd. i spent hours going through different warnings i had - but could not find anything relevant.
4. You run sucsesfully a P&R with Quartus, but after downloding to FPGA the design did not run. Have a look to the resource utilization of your imported blocks. Something strange ( only a few LE or so ...) ? Did you get still warnings regarding .... stuck at ground or VCC . What about timing violations ? Did you achieve the required clock frequency ? the resource utilization looks ok. i do have several stuck at gnd/vcc, but they are from generated stuff (i think from synplifypro) and i don't know why is this, and what caused them.
i also have several latch insertion - because of unsafe behavior - but it happens in a block i created and simulated lots of times. and also - the same block worked in the past. i realize that this might cause problems - and i'm now working on changing that vhdl file so that it won't have this problem.
i also get a timing error - but it has been there from day one, and it is from a part of the gidel generated top file - part of which i don't use.
Can you please post your toplevel ?
it is a problem to attach - it holds a big hierarchy. Have a nice weekend GPK --- Quote End --- thanks again!
