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As I'm using GiDEL card - I have many warnings that are related to their parts of the project (including timing error). But I don't use these parts, they are declared but that's it.
What I see is that all my data outputs from the blocks are stuck at GND,
even though input to it are correct (I used SignalTap to see these results)
I want to remind you that my project was already working - except it didn't hold timing - when I combined the entire project in SynplifyDSP and not in Quartus (meaning - I combined before I synthesized) so I'm somewhat beliving that the problem is somewhere with my usage of the tools - not a design problem... :confused:
But again.. I could be wrong.
Ps - not so much related - is there a way to automatically insert registers? Or must I register manually every connection?
thanks again!
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Hi,
maybe it is now a good time where we should summarize what we know. Please post your comments to my points.
1. You have a project where all is running. In this project you did not split your design,
but you don't get the required clock speed. Is it not possible in SynplifyDSP to add some
pipeline delay in order to speedup the design ?
2. In order to achieve timing closure you split your design and introduced an "external" memory. Is that memory outside of the FPGA or means "external" it is outside your original design ? How did you split the design ?
You run two SynplifyDSP ( generates the VHDL ) and SynplifyPro (generates the vqm files) projects. After that you run two speparate Quartus project in order to synthesis the
two blocks ( necessary due to the module name problems of SynplifyDSP). After that you import the two blocks into your main project as <>.qxp file. You run a simulation for each block using the vqm file generated by SynplifyPro. After solving some problems ( implementation as LE, switch from VHDL to verilog) the simulation shows the expected results.
3. For your main project you need a toplevel. How is it generated ? Did you run a simulation of the main project with the imported blocks included ? Which simulator do use for simulation Quartus or modelsim ?
4. You run sucsesfully a P&R with Quartus, but after downloding to FPGA the design did not work.
Have a look to the resource utilization of your imported blocks. Something strange ( only a few LE or so ...) ? Did you get still warnings regarding .... stuck at ground or VCC .
What about timing violations ? Did you achieve the required clock frequency ?
Can you please post your toplevel ?
Have a nice weekend
GPK
Honored Contributor
