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Altera_Forum's avatar
Altera_Forum
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15 years ago

working with Quartus 8+Synplify DSP + Synplify PRO

Hi all, I'm working on a undergraduate final project, and I use SynplifyDSP to implement a video improvement algorithm. The problem I faced - In my algorithm I have to access external memor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Yes - that is what I meant.

Any other things I should check?

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Hi,

what misbehaviour shows your design running of the FPGA ?

Look into your reports of the main Quartus project. Look for

strange messages ( e.g Latches, Pins stuck ground .... ) and timing violations.

Which simulation do you use ?

Kind regards

GPK