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Altera_Forum's avatar
Altera_Forum
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15 years ago

working with Quartus 8+Synplify DSP + Synplify PRO

Hi all, I'm working on a undergraduate final project, and I use SynplifyDSP to implement a video improvement algorithm. The problem I faced - In my algorithm I have to access external memor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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What output are you referring to?

I used the Verilog implementation, which I converted to VQM, which I then exported as a post synthesis design partition, which I then imported into my main project. Compiled it and loaded to the FPGA.

Simulation I did in Quartus on the "vqm stage".

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Hi,

that means you are running the simulation with the SynplifyPro VQM File. But as far as I understand this only a part of your design. Right ?

Kind regards

GPK