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Hi,
you were right! Using Verilog did helped - the simulation now works as it works when I don't use DSP's at all.
It is strange though - one of the blocks works the same when I implement with DSP's and when with LE's (using VHDL not verilog), but all the others I had to use verilog or LE's only to work :confused:. I guess this is all as a result of some program bugs...
Will wait for the full project synthesis to finish, I hope it would work.
thanks again!
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Hi,
I also guess that you run into some tool bugs. That's why I recommend to try newer tool version. On the other hand when your design is running by using verilog maybe you can stay with this solution.
Kind regards
GPK
Honored Contributor
