working with Quartus 8+Synplify DSP + Synplify PRO

Hi,

you were right! Using Verilog did helped - the simulation now works as it works when I don't use DSP's at all.

It is strange though - one of the blocks works the same when I implement with DSP's and when with LE's (using VHDL not verilog), but all the others I had to use verilog or LE's only to work :confused:. I guess this is all as a result of some program bugs...

Will wait for the full project synthesis to finish, I hope it would work.

thanks again!