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I use SynplifyPRO 9.6.1
SynplifyDSP C-2009.03 SP1
Quartus II version 8 build 231 SP1
SynplifyDSP creates some sort of a VHDL implementation and a SynplifyPRO project (including timing constraints etc).
I then synthesize it in SynplifyPRO to get the VQM file that includes the whole implementation.
Using the LE's the simulation of the block is working, I'm now synthesizing the entire project so I could test it on the FPGA (it takes about an hour of synthesizing...)
So I will update as soon as I'll have answers. For me it is really strange that I cannot simulate with the DSP's, but I can with the LE's - or should I say - when using DSP's something is going wrong and not working, but when using the LE's it does work. :confused:
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Hi,
that are quite old versions of the tools. Maybe you should try newer versions at least for SynplifyDSP and SynplifyPro. Are you using FPGA's which are the first time supported by the tool versions ? My guess is that there is something wrong with the DSP block instanciation in the VHDL file of SynplifyDSP. Maybe you can make a trial by using Verilog
output of SynplifyDSP. For the rest of the flow it makes no difference which language you use.
Kind regards
GPK
Honored Contributor
