Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

working with Quartus 8+Synplify DSP + Synplify PRO

Hi all, I'm working on a undergraduate final project, and I use SynplifyDSP to implement a video improvement algorithm. The problem I faced - In my algorithm I have to access external memor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I use SynplifyPRO 9.6.1

SynplifyDSP C-2009.03 SP1

Quartus II version 8 build 231 SP1

SynplifyDSP creates some sort of a VHDL implementation and a SynplifyPRO project (including timing constraints etc).

I then synthesize it in SynplifyPRO to get the VQM file that includes the whole implementation.

Using the LE's the simulation of the block is working, I'm now synthesizing the entire project so I could test it on the FPGA (it takes about an hour of synthesizing...)

So I will update as soon as I'll have answers. For me it is really strange that I cannot simulate with the DSP's, but I can with the LE's - or should I say - when using DSP's something is going wrong and not working, but when using the LE's it does work. :confused: