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Altera_Forum's avatar
Altera_Forum
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15 years ago

working with Quartus 8+Synplify DSP + Synplify PRO

Hi all, I'm working on a undergraduate final project, and I use SynplifyDSP to implement a video improvement algorithm. The problem I faced - In my algorithm I have to access external memor...
Altera_Forum's avatar
Altera_Forum
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15 years ago

thanks! I did manage to fit the design into the FPGA without using this option, but it is nice to know as I'm now using 100% DSP's so this way I could free up some DSP's for the future...

Anyway, still having problems - My design is just not working!

In SinplifyDSP I get correct results, but when I try it on the FPGA - I get lots of pins stuck at GND.

Using SignalTap I found that it happens after the first block that I did using the above mentioned method. I tried to simulate the vqm in Quartus - and I do get that all my outputs are stuck at GND. No idea why this is...

Is it actually possible to simulate vqm's using the Built in Simulator tool?

(what I need is actually a logic simulation - just to see that my "1+1" equals "2")

And does anyone have any idea why this could happen?

thanks again...

Update:

ok - this is weird... I used the option in SynplifyPRO that forces the implementation in LE's - and simulated in Quartus, and now I don't get the stuck at GND outputs...

Is there a problem simulating DSP's?