New ContributorWorking on exercise #2 and found this error at step 5: "Error (12006): Node instance "lpm_mult_inst" instantiates undefined entity "lpm_mult".
Would you mind show me what causes this error?
Note: I am using Quartus Prime Lite 16.1 to do the exercise that suggests for Quartus® Prime Standard Edition software version 15.1
Below is the piece of code that the error points to.
-- megafunction wizard: %LPM_MULT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_mult
-- ============================================================
-- File Name: mult.vhd
-- Megafunction Name(s):
-- lpm_mult
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2016 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
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--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
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--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY mult IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END mult;
ARCHITECTURE SYN OF mult IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT lpm_mult
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_widtha : NATURAL;
lpm_widthb : NATURAL;
lpm_widthp : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(15 DOWNTO 0);
lpm_mult_component : lpm_mult
GENERIC MAP (
lpm_hint => "MAXIMIZE_SPEED=5",
lpm_pipeline => 2,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_MULT",
lpm_widtha => 8,
lpm_widthb => 8,
lpm_widthp => 16
)
PORT MAP (
clock => clock,
dataa => dataa,
datab => datab,
result => sub_wire0
);
END SYN;
