Honored Contributor
Honored ContributorNo I don't have any memory controllers today.
But I did reserve a bunch of pins for an LPDDR interface (1.8 V), expecting to take advantage of the hard memory controller once I figured out how to instantiate it. My banks are currently defined today as follows: Bank 3A: 3.3v IO (Config and CPU interface) Bank 3B: 3.3v IO (CPU interface) Bank 4A: 3.3v IO (CPU interface) Bank 5A: 3.3v IO (Cpu interface_ Bank 5B: 2.5v IO (Some BLVDS signals defined) Bank 7A: 1.8v IO (Possible Memory Controller plus DDR ADC interface) Bank 8A: 1.8v IO (Possibble Memory Controller) Bank 9A: 3.3v IO (Config pins based on VCCPGM?) Bank GXB_L0 and GXB_L1 (1.1v and 2.5v) (No current logic defined here, but I do have some pins reserved. However the error exists even if I remove all pin assignments. We are looking into changing the CPU interface from 3.3V down to 1.8V but this is more of a power optimization step that we are still evaluating the significance of the board change to make happen. Thanks Pancake.. Pete
