Will Quartus ever support Verilog hierarchical parameter referencing?

I can only suggest you add a parameter at your top level, specifying the pipeline delay, for each module you instantiate. Prior to elaboration, these pipeline delays are know and fixed - you know what modules you're instantiating and associated delays. I appreciate this is only a little better than hard coding these static values into your higher level code. However, it would make for more readable code.