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Altera_Forum's avatar
Altera_Forum
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13 years ago

Why to use a VHDL process for combo logic

Hi everyone, I hope this is the right subforum to post my question.

I've been using VHDL for many months and I can say I usually find my way to get what I need working. However, some days ago a question came to my mind looking at someone else's code. The question is the following:

Is there any advantage in describing a combinational piece of logic (e.g., a multiplexer or a decoder) through a process instead of with concurrent statements only?

Thank you for any suggestion you will give!

Regards,

Lorenzo

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    The real advantage is in well written, well commented code - not whether or not a process is used. Id rather see a well written process that a badly written bit of concurrent code.

    But there is an inherant danger with a process - if you miss a signal from the sensitivity list it will not behave in simulation the same as on real hardware.

    All lines of VHDL outside a process are really just a process sensitve to all signals on the right hand side of the assignment.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thank you for your clear answer: that's exactly what I needed to know.

    Regards,

    Lorenzo