Why to use a VHDL process for combo logic

The real advantage is in well written, well commented code - not whether or not a process is used. Id rather see a well written process that a badly written bit of concurrent code.

But there is an inherant danger with a process - if you miss a signal from the sensitivity list it will not behave in simulation the same as on real hardware.

All lines of VHDL outside a process are really just a process sensitve to all signals on the right hand side of the assignment.