Why TimeQuest add clock constrain automatically?

What is the difference between normal mode, source-synchronous mode, and zero-delay buffer mode?

My design is verilog based, and the clock is generated by another FPGA onboard, which also drives some inputs to cyclone3 and samples outputs from cyclone3. It is a hierarchical design, as you can see there's fifo controller involved. However, I got lost when tracing the critical path, because many signals are difficult (if not impossible) to correlate with rtl.