Why TimeQuest add clock constrain automatically?

If you put the PLL in source synchronous compensation mode(first page of megawizard), then you're correct that they'll be vary close. That doesn't mean the clock delay will be 0, just that your clock delay should match your data delay very closely.

I do see unique names. Hierarchy is pretty much always there, and final node names often have something indicitave of their function, like mux or add in the name. Do you have hierarchy? Is this a schematic?