Why TimeQuest add clock constrain automatically?

Thanks for the explanation.

1) Isn't pad delay the same for all pins? So that should result in net 0 between clk and data. Also 0.63ns delay seems big for cyclone3-6 device.

2) I understand what you are saying, but other synthesis tools ATTACH some unique names to combination logic between two flops instead of making up something that's impossible to decipher.