Honored Contributor
Honored Contributor1) PLLs aren't perfect. (I assume you mean closer to 0.)
2) The PLL doesn't compensate for everything. For example, there is a delay from the input buffer to the PLL which is not part of the feedback path, and therefore can't be 100% compensated for(the delay should be minimal, but the buffer is not). Note that you can try different PLL compensation modes depending on your requirements. To keep signal names, each signal would have to be the output of a LUT. This would generally give very bad synthesis. You can put keep attributes on any nets you really want to keep, but I would avoid this practice as much as possible. Register names are the ones that are generally kept, and I base all my analysis using them at tent-posts between combinatorial logic, accepting that it will be a somewhat undecipherable cloud of logic in between. That's why you can't locate to the RTL view, as they don't match up. (And all synthesis tools work this way. I'm sure there are technical reasons for this, as it's been a bane of the industry. If the combinatorial logic was synthesized/named in a deterministic way, then preserving results, including synthesis, placement and routing, would be much easier...)
