Why TimeQuest add clock constrain automatically?

Why is there non-zero clock network delay even with PLL? For example, I used altpll to generate a 200MHz clock which exactly matches an input clock at chip boundary. However, timequest shows 0.623ns "clock network delay". Isn't PLL supposed to make it 0?

Another question is why does timequest not preserve signal names in the report? For example, it shows "sig~242|dataa", "sig~242|combout", "n|Mux0~1|datac", "n|Mux0~1|combout", "m|fifo|auto_generated|rdptr_g1p|countera9|combout", ... all of these signals are so obscured that the timing report becomes useless. When I tried "Locate->in rtl viewer" on these signals, I got warning "Can't find instance name xxx in current RTL schematic".