Why TimeQuest add clock constrain automatically?

Create a new .sdc from TimeQuest. (It's just a text file). Add:

1) Add the following for each clock coming into the port. Naturally, change the period value, name and I/O port name to match what your design.

create_clock -period 10.0 -name clk100 [get_ports clk100]

2)

derive_pll_clocks

3) If 65nm or newer family, add:

derive_clock_uncertainty

That's a good start. When you're ready, add a set_clock_groups constraint to show which clocks are not related(by default all clocks are related, and so paths between clocks with weird frequnecies like 6.666ns to an 8ns clock won't be analyzed correctly).

When editing, just keep editing the .sdc, then saving, going into TimeQuest and click on:

Reset Design

Report All Summaries

keep repeating until you get what you want. That's the quick 3 minute starter. Read the documentation after that...