Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Why SIPO works in model sim and not in quartus ?

Hi, i'm trying to make a serial in parallel out (SIPO) shift registrer. im actually trying to work with the wolfson WM8731 codec on the DE2 board. Here's my problem, btw im pretty new to his. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello, lespoils.

I'm not familiar with Verilog but I think you should add condition [not(cmpt_Fs == Fs)] to statement:

always @(negedge clk) begin

//compteur de coup de clock

cmpt_Size = cmpt_Size+1;

cmpt_Fs = cmpt_Fs+1;

//shift

input_tempdata <= {input_tempdata,serial_in};

end