Forum Discussion
TRoa
Occasional Contributor
7 years ago1) The pin tags, which means for example this net is connected to that pin number on FPGA. The tags, that are visible on schematic after we assign a particular net to a pin in pin planner.
2) Please see the screen shots provided on this thread in earlier posts. All the nets are connected in pin planner, but only few are visible in Schematic i.e PIN_23 and PIN_105.