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my design using EPC16Q240C8N,and classic time analyizer setup is :tsu=3ns,tco=5ns,tpd=5ns,th=3ns
but look at the picture ,why slack is all -??
and what can i do now?
and ,my main clolck is 66mhz(external connection crystal oscillator),and i set fmax =75mhz
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Hi,
with the setting of tsu,tco,th you specify the timing requirements of devices which drives or are driven by your FPGA. Make sure that this settings are realistic.
Slack means the difference between required and actual value . As long as the value is positive your are fine. Negative value indicates a timing violation.
Fmax is the maximum clock frequency that can be achieved without violating internal time requirements.
Kind regards
GPK