Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

why my tsu is so long?

my design using EPC16Q240C8N,and classic time analyizer setup is :tsu=3ns,tco=5ns,tpd=5ns,th=3ns

but look at the picture ,why slack is all -??

and what can i do now?

and ,my main clolck is 66mhz(external connection crystal oscillator),and i set fmax =75mhz

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Your slack is -ve because your design can't run as fast as you've requested it to.

    You will have to provide more information if you want more help than that.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    and ,my main clolck is 66mhz(external connection crystal oscillator),and i set fmax =75mhz

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Are the failing paths between clock edges of the same clock and is this clock the 66MHz clock?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    What does the Timing Optimization Advisor tell you what you could / should change in your quartus project setup to achieve the desired timing ?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    my design using EPC16Q240C8N,and classic time analyizer setup is :tsu=3ns,tco=5ns,tpd=5ns,th=3ns

    but look at the picture ,why slack is all -??

    and what can i do now?

    and ,my main clolck is 66mhz(external connection crystal oscillator),and i set fmax =75mhz

    --- Quote End ---

    Hi,

    with the setting of tsu,tco,th you specify the timing requirements of devices which drives or are driven by your FPGA. Make sure that this settings are realistic.

    Slack means the difference between required and actual value . As long as the value is positive your are fine. Negative value indicates a timing violation.

    Fmax is the maximum clock frequency that can be achieved without violating internal time requirements.

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    could you please give me a recommend value about tsu,tco,tpd,and th ?

    I am a beginner ,and i dont know how to setup it
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    could you please give me a recommend value about tsu,tco,tpd,and th ?

    I am a beginner ,and i dont know how to setup it

    --- Quote End ---

    Hi,

    difficult to say without knowledge of your system. You have to look to the datasheets of the sources and destinations, in order to to find out their requirments.

    Kind regards

    GPK