Why my outputs in FSM for SPI interface are becoming 'X red' whenever they shall be written with outputs.

Hi, also second process has no edge, so it is async, sensitivity list has no sense how is used as noted from AndyN.

Reset if used on async has no sense on clock event:

							when INIT=>	
								if cs_n='0' and  reset_n ='1' then
								state <= DF;
								else 
								state <= INIT;
								end if;
							

second process has no event so it is Async.

1. process(state, sclk, din, cs_n, clk) is
2. begin
3. case state is
4. when INIT =>
5. -- new_data <='0';
6. counter <= 0;
7. t_bus <= "00100000000000000";
8. -- regnr<="00";
9. -- regwrite_n<='1';
10. -- regcontent<=(others=> '0');

try read this book, you can find an example of SPI and how to code in VHDL.

https://www.scribd.com/document/364557756/Beginning-FPGA-Programming-Metal-Your-Brain-on-Hardware

Hi, clean up code and learn VHDL event.

at second glance, many issue are on your code, don't use elsif with event:

if reset_n ='0' then
  .. reset actions
else
 if rising_edge(clk) then
   .. clock event
 end if; -- clock event
end if; -- reset

Second process:

State is a signal assigned from clock on first process, can be ok but if you wish state be an event remove conflicting rising_edge on midst of code.

First process is event driven from rising edge of same clk.

On SPI need use both rising and falling clock event, derive them from an edge detector or code the right way, receiving on one edge transmitting on the other edge.

I assume this is a slave SPI, so your clock is slow (5MHz) and you own a fast clock too.

Sample SPI on a two/three stage shift register on fast clock then check for rising falling sequence 001 110.

Drive all logic from fast clock using edge detector as clock enable.

Second process as case assignment instead of combinatorial when else need have just case in sensitivity list.

try post cleaned code.

Regards