VALLA
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AndyN
Occasional Contributor
Occasional ContributorYou really need to take a look at your process sensitivity list - there is no way that this would be synthesizable (and may be the cause of your simulation issues). From the looks of your code, I'd say the only thing that should be in your sensitivity list is clk. For this kind of interface, you don't really want to use sclk as a true clock, use it as a signal to tell you when to sample/control the rest of the SPI interface.
RRomano001
Contributor
ContributorHi, also second process has no edge, so it is async, sensitivity list has no sense how is used as noted from AndyN.
Reset if used on async has no sense on clock event:
when INIT=>
if cs_n='0' and reset_n ='1' then
state <= DF;
else
state <= INIT;
end if;
second process has no event so it is Async.
- process(state, sclk, din, cs_n, clk) is
- begin
- case state is
- when INIT =>
- -- new_data <='0';
- counter <= 0;
- t_bus <= "00100000000000000";
- -- regnr<="00";
- -- regwrite_n<='1';
- -- regcontent<=(others=> '0');
try read this book, you can find an example of SPI and how to code in VHDL.
https://www.scribd.com/document/364557756/Beginning-FPGA-Programming-Metal-Your-Brain-on-Hardware
