Why is there no delay in my synthesis results?

A functional, RTL simulation will not show delays. I'm not sure what you mean here with two different simulations "function" and "synthesis". They're the same thing. If you want to see delays in a simulation, you have to perform a post-fit, gate-level simulation. But for typical design verification, use RTL simulation along with timing analysis. For that, you need to create timing constraints in a .sdc file.