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MBaue12's avatar
MBaue12
Icon for New Contributor rankNew Contributor
5 years ago

Why is the maximum frequency lower in performance mode than in any other mode?

Hey there!

I started to learn VHDL development by using a MAX10-FPGA and a small development board.

My first project is to develop a small "distance sensor". The project itself is very small with just 4 simple files and about 300 lines of code.

When I spent some time on investigating the different optimization modes, I figured out that the maximum frequency is lower in performance mode than in any other mode. But shouldn't it be vice versa?!

-> balanced mode:75 LE and maximum frequency of 253,94 MHz

-> Performance mode: 80 LE and maximum frequency of 209,16 MHz

-> Power mode: 75 LE and maximum frequency of 254,26

-> Area: 75 LE and maximum frequency of 253,94 MHz

Does anyone understand what went wrong there? Or are these different modes more reliable in "bigger" applications?

Thanks in advance!

7 Replies

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    Are the design for 4 compilation modes the same? Did you change the HDL before running in different compilation mode? Besides this, you may check if there is any differences between the design for different mode after the compilation.

    Thanks.

    Best regards,

    KhaiY

    • MBaue12's avatar
      MBaue12
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi @KhaiY_Intel​ ,

      thanks for your response!

      The design (vhd-files) is the same for every compilation mode.

      So, I compiled the code and checked the compilation reports.

      After that I changed the optimization mode, recompiled the design and compared the compilation report with the first one.

      There I saw that a different amount of LE is used and the timing analysis shew that the maximum frequency varies from one mode to the other.

      Surprising is that the power-mode is the fastest mode and the performance-mode is the slowest mode.

      Looking on the technology map viewer (post fitting) shows that there are some slight variations between e.g. power- and performance-mode.

      It's unexplainable for me why the compiler worked in this way...

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    The compilation result is different due to different placement and routing in each of the compilation. Do you see any limiting factor in the fmax report?

    What is the software version and edition you are using?

    Thanks.

    Best regards,

    KhaiY

    • MBaue12's avatar
      MBaue12
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi @KhaiY_Intel​ ,

      I'm using Quartus (Quartus Prime 19.1) Lite Edition.

      The fmax report shows just the maximum reachable frequencies and the additional information that all frequencies above 250 MHz are limited to the maximum of 250 MHz.

      There is no further information include what the "bottleneck" could be..

  • skyjuice's avatar
    skyjuice
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    How many seeds did you run for each setting? As there could be 'seed noise', I'd recommend compiling a few seeds for each setting and do an average comparison between them.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    We do not receive any response from you to the previous question/reply/answer that I have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

    Thanks.

    Best regards,

    KhaiY