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MBaue12's avatar
MBaue12
Icon for New Contributor rankNew Contributor
5 years ago

Why is the maximum frequency lower in performance mode than in any other mode?

Hey there! I started to learn VHDL development by using a MAX10-FPGA and a small development board. My first project is to develop a small "distance sensor". The project itself is very small with j...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Are the design for 4 compilation modes the same? Did you change the HDL before running in different compilation mode? Besides this, you may check if there is any differences between the design for different mode after the compilation.

Thanks.

Best regards,

KhaiY

MBaue12's avatar
MBaue12
Icon for New Contributor rankNew Contributor
5 years ago

Hi @KhaiY_Intel​ ,

thanks for your response!

The design (vhd-files) is the same for every compilation mode.

So, I compiled the code and checked the compilation reports.

After that I changed the optimization mode, recompiled the design and compared the compilation report with the first one.

There I saw that a different amount of LE is used and the timing analysis shew that the maximum frequency varies from one mode to the other.

Surprising is that the power-mode is the fastest mode and the performance-mode is the slowest mode.

Looking on the technology map viewer (post fitting) shows that there are some slight variations between e.g. power- and performance-mode.

It's unexplainable for me why the compiler worked in this way...