Why index cannot fall outside?

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I want know why j>=0 is wrong at verilog?

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It's not wrong with Verilog. But loop evaluation fails according to your signal definition reg [3:0] i,j; Verilog numbers are unsigned by default, so j>=0 is always true. Iteration schemes are evaluated at compile time, there is no need to define loop variables as bit vectors. Use an integer type instead.

Assigning dataout_memo in a loop prevents it's implementation as internal RAM. I'm not sure if this is what you intend.