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Altera_Forum
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13 years ago

why error near text "port"; expecting "(", or "'", or "."

Error (10500): VHDL syntax error at Transmit2.vhd(106) near text "port"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at Transmit2.vhd(142) near text ";"; expecting ":=", or "<...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The component instance can be linked to the process by signals, not variables. Variables are only defined inside a process.

At second sight, I noticed several violations of VHDL synatax/semantic rules

- while constructs aren't supported for synthesizable VHDL

- you can't connect multiple output ports to the same signal