Why does this design not fit and how to reason about congestion

The top.fit.summary (good to know about btw!) confirms what you say, the estimate is simply off, a blocksize of 16 will not fit and uses 101% of DSP nodes:

Fitter Status : Failed - Mon May  1 13:24:51 2017
Quartus Prime Version : 16.0.0 Build 211 04/27/2016 SJ Pro Edition
Revision Name : top
Top-level Entity Name : top
Family : Arria 10
Device : 10AX115N3F40E2SG
Timing Models : Final
Logic utilization (in ALMs) : 257,659 / 427,200 ( 60 % )
Total registers : 468262
Total pins : 288 / 826 ( 35 % )
Total virtual pins : 0
Total block memory bits : 4,183,118 / 55,562,240 ( 8 % )
Total RAM Blocks : 227 / 2,713 ( 8 % )
Total DSP Blocks : 1,536 / 1,518 ( 101 % )
Total HSSI RX channels : 8 / 48 ( 17 % )
Total HSSI TX channels : 8 / 48 ( 17 % )
Total PLLs : 18 / 112 ( 16 % )