*Why* does analysis fail (err 17044) for some qsys + ddr projects?

Hello,

I am having this exact same problem. I have a project utilizing a Cyclone V 5CEFA2F23C8N. It has a single Micron MT41K128M16 memory. Had an average sized Qsys project put together and compiled successfully. When I would try to do the Quartus build I would get the following error.

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Error (17044):

Illegal connection found on I/O input buffer primitive poc:

poc|poc_mem_if_ddr3_emif_0:

mem_if_ddr3_emif_0|poc_mem_if_ddr3_emif_0_p0:

p0|poc_mem_if_ddr3_emif_0_p0_acv_hard_memphy:

umemphy|poc_mem_if_ddr3_emif_0_p0_acv_hard_io_pads:

uio_pads|poc_mem_if_ddr3_emif_0_p0_altdqdqs:

dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:

altdq_dqs2_inst|strobe_in.

Source IO poc:

poc|poc_mem_if_ddr3_emif_0:

mem_if_ddr3_emif_0|poc_mem_if_ddr3_emif_0_p0:

p0|poc_mem_if_ddr3_emif_0_p0_acv_hard_memphy:

umemphy|poc_mem_if_ddr3_emif_0_p0_acv_hard_io_pads:

uio_pads|poc_mem_if_ddr3_emif_0_p0_altdqdqs:

dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:

altdq_dqs2_inst|obuf_os_0 also drives out to other destination than the buffer.

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The above is reformatted to see the instances more clearly.

I went ahead and stripped the Qsys project down to nothing more than a clock and the memory... and the top level was just the port definitions and some wires to connect from Qsys instantiation. Still the same error.

I've tried both the hard and soft controllers. still the same error... Cyclone V does not support alt_mem_phy, so I couldn't try that one...

I've compiled with 13.1, 14.0, & 14.1... Still the same error.

I've wiped the database and deleted all of the assignments... Still the same error.

Any help would be appreciated.

david