Why do we need a SignalTapII that stores data on FPGA instead of...

Question

transmitting it to the PC directly?

I am sure that if a system is designed with the idea of interrupts sent to PC through JTAG, than all those thousands of samples can just be transmitted to the PC instead of being stored on the FPGA. I find this rather strange that when an FPGA has such limited resources, we should use them to store our data along with the actual design itself.

Why not design the device to send the data to the PC directly?

altera_forum · Answer

Because the rate at which data can be transfered to the PC is very slow by comparison with the rate at which data can be written to internal memory.

altera_forum · Answer

JTAG typicaly operates at 8 or 24MHz on Altera boards so factor in overhead that doesn't leave much bandwidth to sample in realtime.  Normally if you need real time capture of data you use an external logic analyzer which is capable of keeping up with the data rate.  Pumping that much data continuosly over JTAG makes about as much sense as draining a pool using a milkshake straw :)

altera_forum · Answer

A hand calculation should answer the question. Presume a SignalTap instance acquiring 256 signals at 100 MHz. Makes not less than 26 GBit/s netto data rate. No PC can receive it, not talking about the interface.

altera_forum · Answer

I see. Related to this is the question regarding which tool is more popular and why among:

SignalTapII logic analyzer,

Logic Analyzer interface editor,

and In-System sources and Probes editor. I know something about the first one but not the other ones.

altera_forum · Answer

Here are some thoughts:

SignalTap is most popular especially for beginners who can view their achievement for real. It is easy, but needs care with clock(s) and fpga fmax. Practically not useful for large project testing but only minor debugging.

sources and probes is useful if you want to debug without changing fpga build (for build sensitive cases).

logic analyser Interface editor: never used it but sounds it is external analyser instead of signaltap and so must be far more more powerful and does not need changing fpga build

Forum Discussion

Why do we need a SignalTapII that stores data on FPGA instead of...

6 Replies

Recent Discussions

Is Quartus Prime Pro 22.4 Compatible with Stratix 10 NX Series Device?

Timing analysis - long combinational path

QuartusPro 25.3 Crashed after using the Signal Tap Logic Analyzer

Duplicate_hierarchy_depth / duplicate_register

Automatically added negative node for TDS output doesn't work with Agilex 5